Method of forming split gate memory cells with thinned side edge tunnel oxide

US11362218B2 · kind B2 · utility

Assignee

• Silicon Storage Technology, Inc. · US

Inventors

• Jinho Kim · Seoul, KR
• Elizabeth Cuevas · Los Gatos, US
• Yuri Tkachev · Sunnyvale, US
• Parviz Ghazavi · San Jose, US
• Bernard Bertello · Caubeyres, FR
• Gilles Festes · La Barque, FR
• Bruno Villard · Aix-en-Provence, FR
• Catherine Decobert · Saint-Maximin-la-Sainte-Baume, FR
• Nhan Do · Saratoga, US
• Jean Thiery · Vaucluse, FR

Key dates

• Filing date: Jun 23, 2020
• Grant date: Jun 14, 2022
• Expiry date: Oct 10, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/43

Abstract

A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.