Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor

US11374024B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Rishabh Mehandru · Portland, US
• Gilbert Dewey · Beaverton, US
• Willy Rachmady · Beaverton, US
• Anh Phan · Beaverton, US

Key dates

• Filing date: Dec 27, 2017
• Grant date: Jun 28, 2022
• Expiry date: Feb 3, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/014
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Integrated circuits with stacked transistors and methods of manufacturing the same are disclosed. An example integrated circuit includes a first transistor in a first portion of the integrated circuit, and a second transistor stacked above the first transistor and in a second portion of the integrated circuit above the first portion. The integrated circuit further includes a bonding layer between the first and second vertical portions of the integrated circuit. The bonding layer includes an opening extending therethrough between the first and second vertical portions of the integrated circuit. The integrated circuit also includes a gate dielectric on an inner wall of the opening.