Anh Phan
44Patents
2h-index
50Co-inventors
56Inventor score
Filing activity: Jun 25, 2008 → Jan 22, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11437283B2 | Backside contacts for semiconductor devices | Electricity | 6 | Active |
| US8501626B2 | Methods for high temperature etching a high-K material gate structure | Electricity | 3 | Active |
| US11348916B2 | Leave-behind protective layer having secondary purpose | Electricity | 2 | Active |
| US11257738B2 | Vertically stacked transistor devices with isolation wall structures containing an electrical conductor | Electricity | 1 | Active |
| US11996411B2 | Stacked forksheet transistors | Electricity | 1 | Active |
| US11742346B2 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Electricity | 1 | Active |
| US11640961B2 | III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts | Electricity | 1 | Active |
| US11676966B2 | Stacked transistors having device strata with different channel widths | Electricity | 1 | Active |
| US11367722B2 | Stacked nanowire transistor structure with different channel geometries for stress | Electricity | 1 | Active |
| US11393818B2 | Stacked transistors with Si PMOS and high mobility thin film transistor NMOS | Electricity | 1 | Active |
| US11573798B2 | Stacked transistors with different gate lengths in different device strata | Electricity | 1 | Active |
| US11894372B2 | Stacked trigate transistors with dielectric isolation and process for forming such | Electricity | 0 | Active |
| US11942416B2 | Sideways vias in isolation areas to contact interior layers in stacked devices | Electricity | 0 | Active |
| US11393722B2 | Isolation wall stressor structures to improve channel stress and their methods of fabrication | Electricity | 0 | Active |
| US11616056B2 | Vertical diode in stacked transistor architecture | Electricity | 0 | Active |
| US11342227B2 | Stacked transistor structures with asymmetrical terminal interconnects | Electricity | 0 | Active |
| US12107085B2 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Electricity | 0 | Active |
| US11430814B2 | Metallization structures for stacked device connectivity and their methods of fabrication | Electricity | 0 | Active |
| US11616060B2 | Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure | Electricity | 0 | Active |
| US11374024B2 | Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor | Electricity | 0 | Active |
| US12224202B2 | Forming an oxide volume within a fin | Electricity | 0 | Active |
| US12148806B2 | Stacked source-drain-gate connection and process for forming such | Electricity | 0 | Active |
| US11916118B2 | Stacked source-drain-gate connection and process for forming such | Electricity | 0 | Active |
| US11699637B2 | Vertically stacked transistor devices with isolation wall structures containing an electrical conductor | Electricity | 0 | Active |
| US11605565B2 | Three dimensional integrated circuits with stacked transistors | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.