Vertical semiconductor device with enhanced contact structure and associated methods
US11387325B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Nov 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.