Inventor · San Jose, CA, US

Erwin Trautmann

7Patents
7h-index
7Co-inventors
48Inventor score

Filing activity: Nov 21, 2014 → May 23, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US9275996B2 Vertical semiconductor devices including superlattice punch through stop layer and related methods Electricity 103 Active
US9406753B2 Semiconductor devices including superlattice depletion layer stack and related methods Electricity 98 Active
US9972685B2 Vertical semiconductor devices including superlattice punch through stop layer and related methods Electricity 59 Active
US10777451B2 Semiconductor device including enhanced contact structures having a superlattice Electricity 27 Active
US10879356B2 Method for making a semiconductor device including enhanced contact structures having a superlattice Electricity 18 Active
US11387325B2 Vertical semiconductor device with enhanced contact structure and associated methods Electricity 10 Active
US11664427B2 Vertical semiconductor device with enhanced contact structure and associated methods Electricity 7 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.