Patent · US Active

Testing circuitry and methods for analog neural memory in artificial neural network

US11393546B2 · kind B2 · utility

3Cited by

6References

8Claims

0Family size

Assignee

Silicon Storage Technology, Inc. · US

Inventors

Hieu Van Tran · San Jose, US
Thuan Vu · San Jose, US
Stephen Trinh · San Jose, US
Stanley Hong · Palo Alto, US
Anh Ly · San Jose, US
Steven Lemke · Boulder Creek, US
Nha Thanh Nguyen · Shoreline, US
Vipin Tiwari · Dublin, US
Nhan Do · Saratoga, US

Key dates

Filing date	Sep 12, 2019
Grant date	Jul 19, 2022
Priority date	—
Expiry date	Sep 12, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5006
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.