Isolation wall stressor structures to improve channel stress and their methods of fabrication

US11393722B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Christopher J. Jezewski · Portland, US
• Willy Rachmady · Beaverton, US
• Rishabh Mehandru · Portland, US
• Gilbert Dewey · Beaverton, US
• Anh Phan · Beaverton, US

Key dates

• Filing date: Jan 12, 2018
• Grant date: Jul 19, 2022
• Expiry date: Mar 30, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0158

Abstract

In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.