Smart sampling for block family scan
US11404139B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2020 |
| Grant date | Aug 2, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with at least one threshold scan criterion, and wherein each scan iteration comprises identifying at least one first voltage bin, wherein each first voltage bin is associated with a plurality of read level offsets, identifying, according to a block family creation order, an oldest block family from a plurality of block families associated with the first voltage bin, and updating at least one bin pointer of the oldest block family based on a data state metric of at least one block of the oldest block family.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.