Patent · US Active

Method for partially removing a semiconductor wafer

US11404262B2 · kind B2 · utility

1Cited by

1References

24Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Sophia Friedler · Villach, AT
Bernhard Goller · Villach, AT
Iris Moder · Villach, AT
Ingo Muri · Villach, AT

Key dates

Filing date	Nov 8, 2019
Grant date	Aug 2, 2022
Priority date	—
Expiry date	Feb 19, 2040

Classification

Technology area (CPC H)Electricity
CPC primaryH10D62/111
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10−2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.