Vertically stacked finFETs and shared gate patterning

US11404319B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aaron D. Lilak · Beaverton, US
• Sean T. Ma · Portland, US
• Justin R. Weber · Portland, US
• Rishabh Mehandru · Portland, US
• Stephen M. Cea · Hillsboro, US
• Patrick Morrow · Portland, US
• Patrick H. Keys · Portland, US

Key dates

• Filing date: Aug 24, 2017
• Grant date: Aug 2, 2022
• Expiry date: Jan 26, 2038

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02E10/50
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Stacked finFET structures including a fin having at least a first layer of semiconductor material stacked over or under a second layer of semiconductor material. The first and second layers may include a Group IV semiconductor material layer and a Group III-V semiconductor material layer, for example. A stacked finFET may include an N-type finFET stacked over or under a P-type finFET, the two finFETs may have channel portions within the different semiconductor material layers. Channel portions of the first and second layers of semiconductor material may be coupled to separate gate electrodes that are vertically aligned. Channel portions of the first and second layers of semiconductor material may be vertically separated by subfin portions of the first and second layers. Different layers of dielectric material adjacent to the subfin portions may improve electrical isolation between the channel portions, for example as a source of fixed charge or impurity dopants.