Dielectric isolation layer between a nanowire transistor and a substrate

US11404578B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Bruce Beattie · Portland, US
• Leonard P. GULER · Hillsboro, US
• Biswajeet Guha · Hillsboro, US
• Jun Sung Kang · Hillsboro, US
• William Hsu · Hillsboro, US

Key dates

• Filing date: Jun 22, 2018
• Grant date: Aug 2, 2022
• Expiry date: Dec 2, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-κ”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.