Memory arrays and methods used in forming a memory array
US11411015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2021 |
| Grant date | Aug 9, 2022 |
| Priority date | — |
| Expiry date | Jan 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32134
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising upper conductor material, lower metal material, and intervening metal material vertically between the upper conductor material and the lower metal material. The intervening metal material, the upper conductor material, and the lower metal material are of different compositions relative one another. The intervening metal material has a reduction potential that is less than 0.7V away from the reduction potential of the upper conductor material. A stack comprising vertically-alternating insulative tiers and conductive tiers is formed above the conductor tier. Channel material is formed through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are formed through the stack to the conductor tier. Elevationally-extending strings of memory cells are formed in the stack. Individual of the memory cells comprise the channel material, a gate region that is part of a conductive line in individual of the conductive tiers, and a memory structure laterally between the gate region and the channel material in the individual conductive tiers. Other methods and stru…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.