Patent · US Active

Memory devices, modules and systems having memory devices with varying physical dimensions, memory formats, and operational capabilities

US11416437B2 · kind B2 · utility

2Cited by
2References
23Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 19, 2019
Grant dateAug 16, 2022
Priority date
Expiry dateAug 24, 2040

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C7/1048
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.