Two-stage programming using variable step voltage (DVPGM) for non-volatile memory structures
US11417393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2021 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | Jan 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5624
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for programming a non-volatile memory structure with four-page data, wherein the method comprises, in a first stage, selecting four programmable states of a segment of MLC NAND-type memory cells, programming at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increasing the first step voltage level to a second step voltage level for a single program pulse and according to a pre-determined magnitude, and programming a latter of the at least two neighboring programmable states at the first step voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.