Transistors with channels formed of low-dimensional materials and method forming same
US11417729B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2020 |
| Grant date | Aug 16, 2022 |
| Priority date | — |
| Expiry date | May 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/258
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.