Tzu-Ang Chao
11Patents
1h-index
10Co-inventors
40Inventor score
Filing activity: Apr 1, 2020 → Nov 21, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11860534B2 | Pellicle for an EUV lithography mask and a method of manufacturing thereof | Physics | 2 | Active |
| US12174526B2 | Pellicle for an EUV lithography mask and a method of manufacturing thereof | Physics | 1 | Active |
| US11824106B2 | Semiconductor device and method of fabricating the same | Electricity | 1 | Active |
| US11239354B2 | Semiconductor device and method of fabricating the same | Electricity | 1 | Active |
| US12166113B2 | Semiconductor device and method of fabricating the same | Electricity | 0 | Active |
| US11417729B2 | Transistors with channels formed of low-dimensional materials and method forming same | Electricity | 0 | Active |
| US11854895B2 | Transistors with channels formed of low-dimensional materials and method forming same | Electricity | 0 | Active |
| US11342181B2 | Semiconductor devices and methods of manufacture | Electricity | 0 | Active |
| US12265323B2 | Pellicle for an EUV lithography mask and a method of manufacturing thereof | Physics | 0 | Active |
| US12151213B2 | Method of manufacturing semiconductor devices including the steps of removing one or more of the nanotubes from the stack of nanotubes, and/or removing spacers that surrounds each of the plurality of nanotubes, and forming gate dielectric and/or gate electrode to the nanotubes | Electricity | 0 | Active |
| US11749528B2 | Method of manufacturing semiconductor devices including the steps of removing a plurality of spacers that surrounds each of the plurality of nanotubes into a layer of nanotubes, and forming gate dielectric and/or gate electrode | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.