Memory apparatus and method of operation using triple string concurrent programming during erase
US11423996B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2021 |
| Grant date | Aug 23, 2022 |
| Priority date | — |
| Expiry date | May 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/345
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and arranged in strings. Each of the memory cells is also configured to retain a threshold voltage corresponding to one of a plurality of data states and be erased in an erase operation. A control circuit is coupled to the word lines and the strings and is configured to identify ones of the strings having a faster relative erase speed compared to others of the strings. During the erase operation, the control circuit raises the threshold voltage of the memory cells associated with the ones of the strings having the faster relative erase speed while not raising the threshold voltage of the memory cells associated with the others of the strings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.