Nanosheet transistors with sharp junctions
US11430651B2 · kind B2 · utility
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Key dates
| Filing date | Apr 20, 2018 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Jul 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device and resulting structures having nanosheet transistors with sharp junctions by forming a nanosheet stack over a substrate, the nanosheet stack having a plurality of nanosheets alternating with a plurality of sacrificial layers, such that a topmost and a bottommost layer of the nanosheet stack is a sacrificial layer; forming an oxide recess on a first and a second end of each sacrificial layer; and forming a doped extension region on a first and a second end of each nanosheet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.