Integrated assemblies, and methods of forming integrated assemblies
US11430809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2020 |
| Grant date | Aug 30, 2022 |
| Priority date | — |
| Expiry date | Nov 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.