Internal error correction for memory devices
US11436082B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2021 |
| Grant date | Sep 6, 2022 |
| Priority date | — |
| Expiry date | Jan 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.