Patent · US Active

Data processing engines with cascade connected cores

US11443091B1 · kind B1 · utility

0Cited by

43References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Peter McColgan · Dublin, IE
Baris Ozgul · Dublin, IE
David Clarke · Dublin, IE
Tim Tuan · San Jose, US
Juan J. Noguera Serra · San Jose, US
Goran Bilski · Mölndal, SE
Jan Langer · Chemnitz, DE
Sneha Bhalchandra Date · Santa Clara, US
Stephan Munz · Dublin, IE
Jose Marques · Verneuil-sur-Seine, FR

Key dates

Filing date	Jul 31, 2020
Grant date	Sep 13, 2022
Priority date	—
Expiry date	Jul 31, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.