Error avoidance based on voltage distribution parameters of block families
US11443830B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2021 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Mar 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a first data structure mapping block identifiers to corresponding block family identifiers, a block family associated with the block of the memory device, determining, using a second data structure mapping block family identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block family, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device, and reading, using the determined set of read levels, data from the block of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.