Back-end-of-line interconnect structures with varying aspect ratios
US11444029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2020 |
| Grant date | Sep 13, 2022 |
| Priority date | — |
| Expiry date | Feb 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5386
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes an interlayer dielectric layer, a first set of back-end-of-line interconnect structures disposed in the interlayer dielectric layer, and a second set of back-end-of-line interconnect structures at least partially disposed in the interlayer dielectric layer. Each of the first set of back-end-of-line interconnect structures has a first width and a first height providing a first aspect ratio. Each of the second set of back-end-of-line interconnect structures has a second width and a second height providing a second aspect ratio different than the first aspect ratio. The second width is greater than the first width, and the second height is different than the first height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.