Multi-tier threshold voltage offset bin calibration
US11450391B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Dec 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.