Stacked thin-film transistor based embedded dynamic random-access memory

US11450669B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek A. Sharma · Hillsboro, US
• Juan G. Alzate-Vinasco · Tigard, US
• Fatih Hamzaoglu · Portland, US
• Bernhard Sell · Dresden, DE
• Pei-Hua Wang · Beaverton, US
• Van H. Le · Portland, US
• Jack T. Kavalieros · Portland, US
• Tahir Ghani · Portland, US
• Umut Arslan · Hillsboro, US
• Travis W. Lajoie · Forest Grove, US
• Chieh-Jen Ku · Hillsboro, US

Key dates

• Filing date: Jul 24, 2018
• Grant date: Sep 20, 2022
• Expiry date: Jan 19, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/125
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.