Gate all around I/O engineering
US11450759B2 · kind B2 · utility
0Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Sep 20, 2022 |
| Priority date | — |
| Expiry date | Apr 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.