Platform and method of operating for integrated end-to-end fully self-aligned interconnect process
US11456212B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2020 |
| Grant date | Sep 27, 2022 |
| Priority date | — |
| Expiry date | Jan 11, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.