Memory cells based on vertical thin-film transistors

US11462541B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Juan G. Alzate Vinasco · Tigard, US
• Abhishek A. Sharma · Hillsboro, US
• Fatih Hamzaoglu · Portland, US
• Bernhard Sell · Dresden, DE
• Pei-Hua Wang · Beaverton, US
• Van H. Le · Portland, US
• Jack T. Kavalieros · Portland, US
• Tahir Ghani · Portland, US
• Chieh-Jen Ku · Hillsboro, US
• Travis W. Lajoie · Forest Grove, US
• Umut Arslan · Hillsboro, US

Key dates

• Filing date: Dec 17, 2018
• Grant date: Oct 4, 2022
• Expiry date: Feb 3, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/33

Abstract

Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.