Modified verify in a memory device
US11475967B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | May 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged word lines. The control circuitry is configured to program the memory cells using a multi-pass programming operation which includes a first pass and a second pass. The first pass programs the memory cells to a first number of data states, and the second pass programs the memory cells to a greater second number of data states. For at least one word line, during the second pass, a voltage that is applied to at least one memory cell is reduced from a verify voltage by an offset which is determined as a function of a data state of an adjacent memory cell of an adjacent word line and wherein the first pass but not the second pass has been completed in the adjacent word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.