Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic
US11482270B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Nov 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.