Method for preparing transistor device
US11482419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2020 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Feb 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.