Patent · US Active

Condition code anticipator for hexadecimal floating point

US11487506B2 · kind B2 · utility

0Cited by

10References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Silvia M. Mueller · Altdorf, DE
Petra Leber · Ehningen, DE
Kerstin Claudia Schelm · Stuttgart, DE
Cedric Lichtenau · Stuttgart, DE

Key dates

Filing date	Aug 9, 2019
Grant date	Nov 1, 2022
Priority date	—
Expiry date	Feb 12, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2207/3844
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An aspect includes executing, by a binary based floating-point arithmetic unit of a processor, a calculation having two or more operands in hexadecimal format based on a hexadecimal floating-point (HFP) instruction and providing a condition code for a calculation result of the calculation. The floating-point arithmetic unit includes a condition code anticipator circuit that is configured to provide the condition code to the processor prior to availability of the calculation result.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.