Methods for parity error alert timing interlock and memory devices and systems employing the same
US11487610B2 · kind B2 · utility
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Key dates
| Filing date | May 9, 2018 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Jun 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are described, in which a parity error alert timing interlock is provided by first waiting for a timer to count a configured parity error pulse width value and then waiting for any in-progress memory operations to complete before deasserting a parity error alert signal that was asserted in response to the detection of a parity error in a command or address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.