Integrated circuitry, a method used in forming integrated circuitry, and a method used in forming a memory array comprising strings of memory cells

US11495610B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Collin Howder · Boise, US
• Shyam Surthi · Boise, US
• Matthew Thorum · Boise, US

Key dates

• Filing date: Jul 6, 2020
• Grant date: Nov 8, 2022
• Expiry date: Jan 18, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/35

Abstract

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. Structure independent of method is disclosed.