Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell
US11501813B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2021 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jul 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.