Multi-level vertical memory device including inter-level channel connector

US11502094B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Ruo Fang Zhang · 红钢城街道, CN
• Enbo Wang · Hubei, CN
• Haohao Yang · 红钢城街道, CN
• Qianbing Xu · 红钢城街道, CN
• Yushi Hu · 红钢城街道, CN
• Qian Tao · Singapore, SG

Key dates

• Filing date: Mar 28, 2019
• Grant date: Nov 15, 2022
• Expiry date: Jul 19, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/27

Abstract

A semiconductor device includes a string of transistors stacked along a vertical direction above a substrate of the semiconductor device. The string can include a first substring, a channel connector disposed above the first substring, and a second substring. The first substring includes a first channel structure having a first channel layer and a first gate dielectric structure that extend along the vertical direction. The second substring is stacked above the channel connector, and has a second channel structure that includes a second channel layer and a second gate dielectric structure that extend along the vertical direction. The channel connector, electrically coupling the first and the second channel layer, is disposed below the second gate dielectric structure to enable formation of a conductive path in a bottom region of the second channel layer. The bottom region is associated with a lowermost transistor in the second substring.