Field-effect transistors with asymmetric gate stacks

US11515424B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Said Rami · Portland, US
• Hyung-Jin Lee · Suwon-si, KR
• Saurabh Morarka · Hillsboro, US
• Guannan Liu · Shanghai, CN
• Qiang Yu · Chengdu, CN
• Bernhard Sell · Dresden, DE
• Mark Armstrong · Portland, US

Key dates

• Filing date: Feb 8, 2019
• Grant date: Nov 29, 2022
• Expiry date: Mar 31, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/518
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.