Inventor · Hillsboro, OR, US

Saurabh Morarka

10Patents

0h-index

26Co-inventors

40Inventor score

Filing activity: Sep 26, 2013 → Sep 9, 2022

Most-cited inventions

Patent	Title	Area	Cited by	Status
US11961836B2	FinFET varactor quality factor improvement	Electricity	0	Active
US11482618B2	Methods of forming dislocation enhanced strain in NMOS and PMOS structures	Electricity	0	Active
US11417781B2	Gate-all-around integrated circuit structures including varactors	Electricity	0	Active
US11610995B2	Methods of forming dislocation enhanced strain in NMOS and PMOS structures	Electricity	0	Active
US12382721B2	Integrated circuit structures having cut metal gates with dielectric spacer fill	Electricity	0	Active
US11515424B2	Field-effect transistors with asymmetric gate stacks	Electricity	0	Active
US11107920B2	Methods of forming dislocation enhanced strain in NMOS structures	Electricity	0	Active
US11411110B2	Methods of forming dislocation enhanced strain in NMOS and PMOS structures	Electricity	0	Active
US11869987B2	Gate-all-around integrated circuit structures including varactors	Electricity	0	Active
US10396201B2	Methods of forming dislocation enhanced strain in NMOS structures	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.