Memory tiles in data processing engine array

US11520717B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• David Clarke · Dublin, IE
• Peter McColgan · Dublin, IE
• Zachary Blaise Dickman · Dublin, IE
• Jose Marques · Verneuil-sur-Seine, FR
• Juan J. Noguera Serra · San Jose, US
• Tim Tuan · San Jose, US
• Baris Ozgul · Dublin, IE
• Jan Langer · Chemnitz, DE

Key dates

• Filing date: Mar 9, 2021
• Grant date: Dec 6, 2022
• Expiry date: Mar 9, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/28
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory tile.