Managing an adjustable write-to-read delay of a memory sub-system
US11526295B2 · kind B2 · utility
1Cited by
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20Claims
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Key dates
| Filing date | Jul 21, 2020 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Jul 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first operating characteristic and a second operating characteristic of a memory sub-system are determined. A write-to-read delay time is set in view of the first operating characteristic and the second operating characteristic. A read operation associated with a memory unit is executed following a period of at least the write-to-read delay time from a time of an execution of a write operation associated with the memory unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.