Multiple spacer patterning schemes

US11527408B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Tzu-shun Yang · Milpitas, US
• Rui Cheng · San Jose, US
• Karthik Janakiraman · San Jose, US
• Zubin Huang · Santa Clara, US
• Diwakar Kedlaya · San Jose, US
• Meenakshi GUPTA · San Jose, US
• Srinivas Guggilla · San Jose, US
• Yung-Chen Lin · Los Angeles, US
• Hidetaka Oshio · Tokyo, JP
• Chao-Sung Li · Santa Clara, US
• Gene Lee · San Jose, US

Key dates

• Filing date: May 5, 2020
• Grant date: Dec 13, 2022
• Expiry date: May 5, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76816
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.