Patent · US Active

Vertical bond-wire stacked chip-scale package with application-specific integrated circuit die on stack, and methods of making same

US11538746B2 · kind B2 · utility

0Cited by

2References

17Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zhicheng Ding · Shanghai, CN
Yong She · Shanghai, CN
Bin Liu · Fishers, US
Aiping Tan · Shanghai, CN
Li Deng · Shanghai, CN

Key dates

Filing date	Dec 23, 2016
Grant date	Dec 27, 2022
Priority date	—
Expiry date	Jan 10, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2225/06575
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.