Etching metal during processing of a semiconductor structure

US11557487B2 · kind B2 · utility

Assignee

• TOKYO ELECTRON LIMITED · JP

Inventors

• Roberto C. Longo Pazos · Austin, US
• Peter Ventzek · Austin, US
• Alok Ranjan · Austin, US

Key dates

• Filing date: Jun 4, 2021
• Grant date: Jan 17, 2023
• Expiry date: Jun 4, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32139
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In certain embodiments, a method of processing a semiconductor structure includes forming a patterned layer over a copper layer to be etched. The copper layer is disposed over a substrate. The method includes patterning the copper layer, using the patterned layer as an etch mask, by performing a cyclic etch process to form a recess in the copper layer. The cyclic etch process includes forming, in a first etch step, a passivation layer on an exposed surface of the copper layer by exposing the exposed surface of the copper layer to a chlorine gas. The passivation layer replaces at least a portion of a surface layer of the copper layer. The cyclic etch process includes subsequently etching, in a second etch step, the passivation layer using a first plasma that includes a noble gas. Each cycle of the cyclic etch process extends the recess in the copper layer.