Interconnect architecture with silicon interposer and EMIB

US11557541B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• MD Altaf Hossain · Portland, US
• Ankireddy Nalamalpu · Portland, US
• Dheeraj Subbareddy · Santa Clara, US
• Robert Sankman · Phoenix, US
• Ravindranath V. Mahajan · Chandler, US
• Debendra Mallik · Chandler, US
• Ram Viswanath · Phoenix, US
• Sandeep B. Sane · Chandler, US
• Sriram Srinivasan · Sammamish, US
• Rajat Agarwal · Portland, US
• Aravind Raghavendra Dasu · Milpitas, US
• Scott J. Weber · Piedmont, US
• Ravi Prakash Gutala · San Jose, US

Key dates

• Filing date: Dec 28, 2018
• Grant date: Jan 17, 2023
• Expiry date: May 19, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H05K2201/10734
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.