Memory devices with four data line bias levels

US11562791B1 · kind B1 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Hao Thai Nguyen · San Jose, US
• Tomoko Ogura Iwasaki · San Jose, US
• Erwin E. Yu · San Jose, US
• Dheeraj Srinivasan · San Jose, US
• Sheyang Ning · San Jose, US
• Lawrence Celso Miranda · San Jose, US
• Aaron Yip · Los Gatos, US
• Yoshihiko Kamata · Yokohama, JP

Key dates

• Filing date: Aug 9, 2021
• Grant date: Jan 24, 2023
• Expiry date: Aug 9, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/5671
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Memory devices might include a first latch to store a first data bit; a second latch to store a second data bit; a data line selectively connected to the first latch, the second latch, and a string of series-connected memory cells; and a controller configured to bias the data line during a programing operation of a selected memory cell. The controller may with the first data bit equal to 0 and the second data bit equal to 0, bias the data line to a first voltage level; with the first data bit equal to 1 and the second data bit equal to 0, bias the data line to a second voltage level; with the first data bit equal to 0 and the second data bit equal to 1, bias the data line to a third voltage level; and with the first data bit equal to 1 and the second data bit equal to 1, bias the data line to a fourth voltage level.