Patent · US Active

Data processing engine arrangement in a device

US11573726B1 · kind B1 · utility

0Cited by

43References

8Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Juan J. Noguera Serra · San Jose, US
Goran H K Bilski · Mölndal, SE
Jan Langer · Chemnitz, DE
Baris Ozgul · Dublin, IE
Richard L. Walke · Edinburgh, GB
Ralph D. Wittig · Menlo Park, US
Kornelis A. Vissers · Sunnyvale, US
Christopher H. Dick · San Jose, US
Philip B. James-Roxby · Longmont, US

Key dates

Filing date	Nov 13, 2020
Grant date	Feb 7, 2023
Priority date	—
Expiry date	Feb 9, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/7807
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.