Memory apparatus and method of operation using periodic normal erase dummy cycle to improve stripe erase endurance and data retention
US11574693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Jun 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.