Modular gated multiplier circuitry and multiplication technique
US11586445B2 · kind B2 · utility
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4References
20Claims
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Key dates
| Filing date | Nov 27, 2019 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Apr 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0207
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are related to a device having multiplier circuitry with an array of summation result cells that holds summation bit values for shifted arrays added together. The device may include latch circuitry having one or more gated elements disposed between the summation result cells, and the gated elements may be adapted to provide a portion of the summation bit values based on a gating signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.