Multiple dies hardware processors and methods
US11586579B2 · kind B2 · utility
0Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Oct 28, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.