Bonded semiconductor die assembly containing through-stack via structures and methods for making the same
US11587920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Aug 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B80/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.